Not applicable.
Not applicable.
This invention is in the field of integrated circuits, and is more specifically directed to the construction of field-effect transistors used in such circuits.
A continuing trend in the field of electronic integrated circuits is the reduction in transistor feature size. These smaller feature sizes enable a higher level of functionality for the integrated circuit, and also significantly reduce the manufacturing cost of the circuit. The manufacturing cost is reduced not only by increasing the number of integrated circuit dies that may be fabricated on a single wafer (and thus for substantially the same cost), but also by increasing the theoretical yield of the wafer for a given defect density by reducing the area affected by a single xe2x80x9ckillingxe2x80x9d defect. Additionally, the performance of the integrated circuit generally improves along with the faster switching times provided by smaller transistors.
The reduction in transistor feature sizes has necessitated, in many instances, a reduction in the operating voltages applied to the integrated circuit, because many of the device breakdown voltages are lower for smaller devices. For example, a smaller channel length in a metal-oxide semiconductor (MOS) transistor generally translates into a lower source-to-drain breakdown voltage. Additionally, reduction in lateral transistor feature sizes, such as channel lengths and electrode widths, generally also necessitates reduced junction depths and other vertical features.
Some integrated circuit applications still require high voltage operation, however. For example, the use of integrated circuits in motor control and automotive applications may require high-voltage output signals, because of the load requirements of such devices. Additionally, some environments may also require integrated circuits to be able to withstand high bias voltages. Accordingly, modern integrated circuits utilizing extremely small active devices and transistors are not directly suitable for these applications.
In the past, separate xe2x80x9cpowerxe2x80x9d integrated circuits were used in combination with low-voltage high-performance integrated circuits in high-voltage applications. In this way, the high-performance integrated circuits could control the power ICs, which in turn would sink and source the high voltage or high current signals required by the application. Of course, for purposes of cost reduction, reduced form factor, and performance, it is desirable to integrate as much functionality as possible into the same integrated circuit. As a result, many modem integrated circuits include both high-performance (or xe2x80x9clow-voltagexe2x80x9d) and high-voltage transistors.
However, the manufacturing processes required for integrating both high-performance and high-voltage transistors into the same integrated circuit can become quite complicated. It has been observed, in connection with the present invention, that the differences in construction between conventional low-voltage and high-voltage transistors do not permit optimization of both transistors in the same process. These differences are particularly dramatic in the formation of the wells into which the transistors are formed. As a result, conventional manufacturing flows utilize separate processes for the fabrication of low-voltage and high-voltage transistors.
Referring now to FIGS. 1a and 1b, the construction of a conventional high-performance, or xe2x80x9clow-voltagexe2x80x9d, p-channel MOS transistor is illustrated in plan and cross-sectional views, respectively. In this example, the transistor is formed at a surface of p-type substrate 2, on which p-type epitaxial layer 3 is formed in the conventional manner. The transistor is formed into n-well 4, which serves as the body region of the MOS transistor. Field oxide structures 5, which may be either conventional LOCOS thermal silicon oxide or silicon oxide deposited into recesses etched into the surface, define the active regions of the device. Polysilicon gate electrode 10 is disposed over a selected location of this active region, and p+ diffused regions 6 are formed into n-well 4 at locations not covered by field oxide structure 5 and gate electrode 10; as a result, p-type source and drain regions of the transistor are formed in a self-aligned manner relative to gate electrode 10. Sidewall filaments may be provided on the sides of gate electrode, if desired, to facilitate later silicidation of the structure and to permit the formation of graded source-drain junctions (typically more appropriate for n-channel devices). Following the deposition of multilevel insulator 7 (which is not shown in FIG. 1a to permit viewing of the structure) and the etching of contact openings through this film, metal conductors 8 may be formed in the conventional manner to make contact to the desired elements of the transistor. In this example, metal electrodes 8s and 8d make contact to the source and drain of the transistor, respectively, while metal electrode 8bg makes a xe2x80x9cback-gatexe2x80x9d contact (also referred to as a xe2x80x9cbodyxe2x80x9d contact) to well 4 via n+ diffused region 9, so that the body region of the device may be biased to a desired voltage.
Several features of the transistor of FIGS. 1a and 1b are specific to low-voltage, high-performance, devices. Generally, n-well 4 will be relatively shallow, and relatively heavily doped (although not as heavily doped as source-drain regions 6). For example, in a conventional sub-micron process, n-well 4 may be on the order of two microns deep into epitaxial layer 3, and may have a doping concentration of on the order of 3xc3x971016 cmxe2x88x923 resulting in a sheet resistance of on the order of 850 xcexa9/square. By making n-well 4 to be relatively shallow and heavily-doped, short-channel-length transistors formed in well 4 can have relatively high gain values of gm (or kxe2x80x2), and this will have quite high performance. In addition, this construction permits excellent transistor matching behavior, as is necessary for precise applications such as current mirror circuits.
However, the heavy doping of n-well 4 necessary for high transistor gain results in relatively low breakdown voltages. For example, the transistor of FIGS. 1a and 1b can have a source-drain breakdown voltage of on the order of five volts or lower. Additionally, the heavy doping of n-well 4 can limit the junction breakdown voltage at its interface with epitaxial layer 3 to as low as 25 volts or lower. While these breakdown voltages are well-suited for many high-speed circuit applications, some motor control and automotive applications cannot be implemented using such devices.
FIG. 2a and 2b illustrate the construction of a high-voltage transistor, for which the breakdown voltages are significantly higher than in the case of the low-voltage transistor described above. This high-voltage transistor has many common features with the transistor of FIGS. 1a and 1b, including p+ diffused regions 16 and n+ diffused region 17, the locations of which are defined by field oxide structures 5 and gate electrode 18. Gate electrode 18 is significantly wider (from source-to-drain) than gate electrode 10 in the low-voltage transistor, providing a longer channel length and thus a higher source-drain breakdown voltage (e.g., on the order of ten to fifteen volts). This longer channel length is acceptable for this device, considering that transistor gain is not a major concern for high-voltage transistors. Metal electrodes 8bg, 8s, 8d are provided to make contact to the body node, source, and drain respectively.
The high-voltage transistor is also similarly formed into substrate 2 and epitaxial layer 3. However, n-well 14 is significantly more lightly doped, and also deeper, than the corresponding n-well 4 in the low-voltage device. For example, n-well 14 may have a doping concentration of on the order of 4xc3x971015 cmxe2x88x923, resulting in a sheet resistance of on the order of 2150 xcexa9/square; the depth of n-well 14 may be on the order of 4 to 5 microns, which is approximately twice as deep as in the low-voltage device. In some applications, n-type buried layer 19 may also be provided beneath the high-voltage transistor; this region is not necessary to the operation of the high-voltage transistor, but if such a buried layer is otherwise available (e.g., as a buried collector for bipolar transistors implemented in the same integrated circuit), layer 18 may be incorporated into the high-voltage transistors as shown in FIG. 2b. 
The deeper and more lightly-doped n-well 14 results in a significantly higher body-to-substrate breakdown voltage than in the case of the low-voltage devices. For example, a high-voltage transistor constructed as described above may have a substrate breakdown voltage of on the order of 60 volts. However, this deep lightly-doped well significantly affects the performance of the device, greatly reducing the gain characteristics. As a result, these high-voltage devices are not suitable for use in performance-critical circuit locations. Additionally, the light doping of the well inserts a significant amount of variability into the construction of the high-voltage device, such that high-voltage devices fabricated in the same die do not match one another as well as low-voltage transistors.
Because of the dichotomy between the performance and breakdown characteristics presented by conventional low-voltage and high-voltage transistors, the circuit design must be careful to not require high-performance or closely-matched transistors in locations that may receive high bias voltages (either across source-drain or between the body region and substrate). These constraints may, in some cases, only be met by sacrificing circuit performance. However, the particular circuit may not be sufficiently robust to tolerate such optimization.
It is therefore an object of the present invention to provide a high-voltage transistor having an increased body-to-substrate breakdown voltage.
It is a further object of the present invention to provide such a transistor that can be constructed using existing process operations.
It is a further object of the present invention to provide such a transistor that is suitable for use in a circuit utilizing precise matched devices in a high voltage environment.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into an integrated circuit that includes both high-voltage devices and at least one low-voltage, high-performance device. The low-voltage device is formed into a well that includes a shallow, heavily doped well formed into the deep, lightly-doped n-well. Other low-voltage devices not subject to high bias voltages, and other high-voltage devices, are formed into their own wells, namely the conventional shallow, heavily doped well for low-voltage transistors, and the deeper, more lightly-doped well for high-voltage devices.